The present disclosure relates to minimizing laminate substrate warpage. More particularly, the present disclosure relates to analyzing a pair of conductive layers included in the laminate substrate and removing conductive material from one of the paired conductive layers according to the layout of the other paired conductive layer.
Laminate substrates are designed for electrical functionality and typically include a glass fiber reinforced core; “top” and “bottom” conductive layers; and top/bottom dielectric layers that are placed between the conductive layers. The conductive layers include a conductive material (e.g., copper) that is circuitized during fabrication according to each layer's corresponding design. The top conductive layers are typically utilized for signal routing (wiring layers) and the bottom conductive layers are typically utilized as power layers (voltage and ground).
Laminate warpage results when a different bending resistance and/or bending force exists above and below the laminate substrate's core. A coefficient of thermal expansion (CTE) mismatch between the dielectric layers and the copper remaining on the conductive layers and dielectric cure shrinkage during fabrication are driving forces for bending as the temperature changes, such as during module assembly operations or during laminate fabrication.